1. Field of the Invention
The present invention relates to an image sensing apparatus having a sensor block with a photoelectric conversion function and a signal processing block for processing a signal from a pixel unit.
2. Related Background Art
Some sensors have a sensor block and signal processing block integrated on a single semiconductor substrate. The sensor block has a pixel unit comprising a plurality of pixels each having a light-receiving element such as a photodiode and a scanning unit for selecting a pixel of the pixel unit, and the signal processing block has an amplifier and the like for processing a signal output from the sensor block. A sensor whose pixel unit is formed by a CMOS process is called a CMOS sensor.
In recent years, a demand for image sensing apparatuses having wide dynamic ranges, high S/N ratios, and low power consumption has arisen for application to digital cameras.
In a conventional sensor that has a sensor block having a pixel unit and scanning unit for selecting a pixel, and a signal processing block for processing a signal output from the sensor block, a single power source is used. If the signal processing block takes priority, the power supply voltage of the sensor block must be reduced to assure operation of this block. As a result, the dynamic range is sacrificed.
A buried photodiode used for, e.g., a CCD can obtain a signal with a high S/N ratio. However, the photodiode generally uses a high power supply voltage, and this results in an increase in clock noise of the signal processing block. As the power supply voltage becomes high, the electric field applied to each MOS transistor (insulated gate transistor) of the signal processing block becomes high. For this reason, impact ionization readily occurs, and noise charges due to this phenomenon reach the sensor block. Especially a pixel unit using a buried photodiode easily generates this noise because of the high power supply voltage.
When a power supply voltage equal to that of the sensor block is used for the signal processing block, the power consumption increases because of the high power supply voltage of the latter block.
A conventional image sensing apparatus has functional processing blocks including a sensor processing system for receiving light from an object and photoelectrically converting the light, a data processing system for sampling/holding an electrical signal from the sensor processing system, to perform shading processing, and for A/D-converting the signal to perform clamp processing or gamma processing, an AE/AF processing system for setting the automatic exposure time and automatic focusing/distance measurement before image sensing, and an output processing system for outputting an appropriate image signal to an output apparatus such as a display, printer, or recording medium.
Some image sensing apparatuses also have a release function for iris selection or a display processing system such as a liquid crystal display.
For a solid-state image sensing apparatus having these processing systems, to reduce consumption of the power source as a limited resource is a longtime challenge. This demand is particularly strong for an apparatus using a battery as a power source. However, a conventional image sensing apparatus has only one power switch, and power consumption is turned on/off at once whenever the user turns on/off the power switch at appropriate times.
A prior art of this image sensing apparatus will be described with reference to FIG. 1. Referring to FIG. 1, when the image sensing start button of an operation unit 60 is depressed, a system control unit 58 detects an image sensing start signal and supplies a trigger signal and clock signal to activate a sensor drive circuit 43 and also causes an image sensor 42 to detect an image sensing signal and output it. This image sensing signal is supplied to an AE/AF processing unit 56 to set an appropriate exposure amount and adjust the focal length to set the lens at the in-focus position. The image sensing signal obtained by the image sensor 42 is converted into a digital signal by an A/D conversion unit 46 in accordance with an instruction from the system control unit 58. A DSP 47 processes the digital signal by shading processing or gamma processing using a memory 48. An encoder 51 is triggered by the system control unit 58 to convert the signal into an image signal compatible with an output apparatus such as a communication system, recording system, or still image printing system, and output the image signal to a corresponding output apparatus 61. The circuits of this image sensing apparatus are designed such that the system control unit 58 repeats a predetermined operation in accordance with the operation of the operation unit 60, and each block starts operation in accordance with an instruction from the system control unit 58. To achieve lower power consumption, the blocks themselves must be designed to have low power consumption.
Japanese Patent No. 2566402 aiming at reduction of power consumption of an image sensing apparatus discloses an information processing apparatus which is provided in a camera to receive and output information for setting image sensing conditions during a clock signal supply period. This information processing apparatus has a main switch manually set at the first position when the camera executes the main operation associated with image sensing or at the second position otherwise, a time count means for measuring a first time when the main switch is at the first position and measuring a second time longer than the first time when the main switch is at the second position, and a gate means for inhibiting supply of the clock signal to the information processing apparatus until the first or second time is counted by the time count means.
On the basis of the state of the information processing apparatus, the time in which supply of the clock signal for information processing is inhibited can be automatically changed in accordance with the state of the main switch. Additionally, the number of times information processing is executed can be decreased in accordance with the purpose intended. Hence, the power consumption can be reduced.
In association with an information processing apparatus such as a personal computer, Japanese Laid-Open Patent Application No. 5-333976 discloses an information processing apparatus having a CPU operated by a clock signal supplied at a frequency that changes depending on the state, a ROM, and a RAM. This information processing apparatus has a means for changing some or all voltages supplied to the CPU, ROM, and RAM in correspondence with the frequency of the clock signal supplied to the CPU. With this arrangement, the operation speed of the CPU can be controlled in accordance with a software instruction. In addition, the supply voltages to the various devices can be controlled. Hence, the power consumption of the information processing apparatus can be reduced.
In a conventional image sensing apparatus, however, even processing systems that are not in use are always turned on or off, resulting in wasteful power consumption.
Furthermore, turning on/off the power source readily generates noise. This may adversely affect display or recording of an image signal.
A general image sensing apparatus is repeatedly powered on/off. This may result in an operation clock shift between processing systems, so undesired image sensing data may be generated because of a synchrony.
The image sensing apparatus has an image sensor unit for sensing an object image, image sensing signal processing unit, AE/AF processing system for computing to achieve the automatic exposure setting function (AE)/automatic focus setting function (AF), and output processing unit. Along with a recent progress in semiconductor technology, normally, a clock signal is supplied to various units to synchronize the operation of each unit and remove time loss.
When supply of the clock signal is stopped, the operations of the units stop. Only the floating current flows to each unit, and the total current is reduced. The power consumption can be reduced by stopping supply of the clock signal. As one prior art, Laid-Open Patent Application No. 9-55890 discloses a “solid-state image sensing apparatus” which stops the driving clock group of a sensor scanning circuit during a period other than the effective image signal period to reduce the power consumption.
Alternatively, it is well known that the clock frequency may be changed to reduce the power consumption of the processing circuit. The power consumption increases in proportion to the clock frequency. As another prior art, Japanese Patent Application Laid-open No. 9-236843 discloses a “solid-state image sensing apparatus” which decreases the number of electron shutter pulses boosted in accordance with the light amount to reduce the power consumption.
Japanese Patent Application Laid-open No. 5-54955 discloses an apparatus which independently selectively supplies a predetermined clock to each functional block. Japanese Patent Application Laid-open No. 5-252417 discloses an apparatus which switches the clock frequency between the blanking period and the effective image period in accordance with a blanking signal. Japanese Patent Application Laid-open No. 5-252477 discloses an apparatus which selects one of two kinds of clocks in accordance with the operation mode of a VTR to selectively operate circuits. Japanese Patent Application Laid-open No. 5-333976 discloses an apparatus capable of changing some or all of the clock frequency to the CPU and supply voltages to various devices. Japanese Patent Application Laid-open No. 8-179847 discloses an apparatus for selectively supplying a plurality of clocks with different frequencies on the basis of the information of each functional block. Japanese Patent Application Laid-open No. 10-124169 discloses an apparatus which controls the frequency of the operation clock of the I/O controller or stops the clock in synchronism with the CPU.
Also, the entire system may be set in accordance with the operation frequency of a processing circuit that has the lowest processing load. More specifically, an apparatus having a plurality of processing circuits independently designed is operated in accordance with the lowest one of the clock frequencies of the processing circuits, thereby reducing the power consumption.
An appropriate frequency of a clock signal is set taking balance between reduction of power consumption and operation of the apparatus. However, even when clock frequencies are independently controlled, processing systems that do not function in a given operation mode also always operate at the maximum frequency, and the entire system consumes wasteful power. Even when the clock frequency of the sensor is made low for clock thinning-out, the data processing system including an A/D converter and DSP (Digital Signal Processor: processor dedicated to digital signal processing) as peripheral devices continues its high-speed operation, resulting in wasteful power consumption.
Even if the operation frequency of the entire system is set low, the clock frequency is limited to the low frequency even in processing which does not use the corresponding circuit. For this reason, the operation performance of the entire system degrades.